This course is a detailed examination of Controller Specification forms to allow Transport Modellers to extract accurate information for modelling and assist Traffic Signal Design Engineers in preparing Traffic Signal Controller Specifications. It is based on the TOPAS 2500 Specification (formerly TR 2500/TR2210A/MCE0141) for microprocessor traffic controllers. Using a real world example the course takes delegates through an ITS1827D document considering all the elements which make up a Specification with theory breaks covering Phase Delays, Detection, Controller Logic, UTC, VA, CLF, Call Cancel Loops, Shuttle Working, SDE/SA, Hurry Calls, Priority/Emergency Modes, Pedestrian Linking and Cross Stream Linking.

Who should attend.

This course will benefit both Transport Modellers and Traffic Signal Design Engineers

Prerequisites.

Prior to attending the course, Delegates should have a basic understanding of traffic signal terminology such as Phases, Stages and Intergreens.

Course content.

• Purpose of the specification. History of the specification and structure of the associated document
• Introduction to the ITS1827D forms and associated spreadsheet
• Working up and interpreting ITS1827D data
• Introduction to the study junction
• Examination of the Forms 1 to 13
• Each form in order with examination of start-up sequence and starting intergreen and a theory break for Phase Delays, Detection and Controller Logic
• Boolean Logic Workshop Exercise
• Using the study junction to work up Boolean Logic for UTC, CLF and VA
• Examination of the Forms 14 to 21
• Each form in order with theory breaks for Call/Cancel Loops, Shuttle Working, SDE/SA and CLF
• Examination of the Forms 22 to 33
• Each form in order with theory breaks for Hurry Calls, Priority/Emergency Modes, Pedestrian and Cross Stream Linking and LRT detectors